NOC DV Sr Lead Engineer
Core
Lead Digital Verification (DV) Engineer responsible for planning, implementing, and owning verification flows for next-generation Infrastructure IPs (DDRSS, Memory Controllers) in System-on-chip (SoC) for smartphones and tablets.
Role type
Senior IC Digital Verification Architect/Engineer
Builds
Infrastructure IPs for System-on-chip (SoC)
Domain
Semiconductor / Hardware Engineering / Digital Verification
Required skills
UVM, System Verilog, ARM bus protocols, SoC system architecture, Functional Coverage, Assertion, Scoreboards, Checkers, Debugging, Regression Signatures, Python, Perl, C/C++, SystemC
Preferred skills
Low power design optimization, Automotive Safety Integrity Levels (ASIL), Post-silicon bring-up, HW-SW debug, Silicon debug tool chains
Technologies
UVM, System Verilog, Certitude, VC Formal, VPlan, Python, Perl, C/C++, SystemC
Responsibilities
Own DV test bench and associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage); Develop test plans and test cases to cover design feature sets; Coordinate with Design and SOC teams on failure debugs and coverage closure; Debug regression signatures and identify bug fixes; Develop and deploy scripts/tools for validation; Debug and root cause post-silicon issues; Work with SoC level performance modeling team on latency and bandwidth analysis.
Seniority
Senior, hands-on IC
