SoC Infrastructure/NoC, Power & Performance Validation Engineer
Core
Pre-silicon emulation and post-silicon validation of SoC bus architecture, performance, and power, focusing on interconnects, QoS, latency, and throughput.
Role type
Senior IC SoC Infrastructure/NoC, Power & Performance Validation Engineer
Builds
SoC silicon with validated interconnects, power efficiency, and performance characteristics
Domain
Semiconductor / SoC Design / Digital Hardware
Required skills
NoC/AXI/_AHB interconnect architecture, FIFO design, performance validation planning, low power modes, dynamic clock/voltage scaling, interrupt architecture, JTAG/debug architecture, performance monitor architecture, CPU/DDR/Multimedia/GPU concepts, memory hierarchy/coherency, C/C++/Python/Assembly, driver/test content design, low-level debugging, power analysis (static/leakage/dynamic), Generative AI for workflows
Preferred skills
Experience leveraging Generative AI technologies for optimizing workflows
Technologies
JTAG, kernel debuggers, C, C++, Python, Assembly, NoC, AXI, AHB
Responsibilities
Write programs to stress interconnect transactions for coverage, develop performance validation plans, analyze SoC bandwidth/QoS/latency/throughput, debug low-level software and hardware issues, validate power-performance trade-offs
Seniority
Senior, hands-on IC
