#Digital Hardware Engineer
Core
Design and verify complex wireless systems, specifically the 6G physical layer, for a Test Base Station (TBS) to validate mobile chipset functionality.
Role type
Digital Hardware Engineer (FPGA/SOC)
Builds
Test Base Station (TBS) hardware and verification infrastructure for Qualcomm mobile chipsets
Domain
Wireless telecommunications / 6G physical layer / FPGA/SOC design
Required skills
RTL/HDL design (VHDL, Verilog, System Verilog), FPGA/ASIC design, HDL Design Verification (DV), high-speed interfaces (PCIe, Ethernet, UCIE), SOC interconnect standards (AXI, AHB, AMBA, Wishbone, JREG, Avalon), Linux development environment
Preferred skills
FPGA vendor tool suites, signal processing, digital communications, wireless physical layer specifications, version control (Git), Python programming, C/C++/Matlab, High Level Synthesis (HLS), embedded software design (RTOS, embedded Linux), Agentic AI frameworks
Technologies
FPGA, SOC, VHDL, Verilog, System Verilog, PCIe, Ethernet, UCIE, AXI, AHB, AMBA, Wishbone, JREG, Avalon, Linux, Python, C, C++, Matlab, Git, HLS, RTOS
Responsibilities
Develop, document, and achieve product development milestones; translate systems requirements into efficient digital implementations; present design reviews to cross-disciplinary teams; support commercialization of new hardware and features
Seniority
Mid-level, hands-on IC
