DV Power Vectors & Window Extraction Engineer (Staff/Sr Staff)
Core
Develop and execute Design Verification (DV) power vectors, analyze waveforms, and extract power windows for simulation, emulation, and silicon validation.
Role type
Staff/Sr Staff Design Verification Engineer (Power Analysis)
Builds
Power-aware verification environments, power vectors, and power analysis windows for SoC chips.
Domain
Semiconductor hardware design and verification
Required skills
Design Verification, power-aware verification, vector development, power analysis, waveform debugging, RTL simulation, SystemVerilog/UVM, low-power concepts, scripting (Python/Perl/Shell/Tcl), waveform analysis tools
Preferred skills
UPF power-intent verification, SoC subsystem power behavior, dynamic voltage drop/IR-drop analysis, emulation platforms, pre-silicon/post-silicon correlation
Technologies
SystemVerilog, UVM, Python, Perl, Shell, Tcl, GLS, emulation platforms
Responsibilities
Develop and execute DV power vectors covering key workloads, power states, transitions, boot flows, retention, reset, and stress scenarios. Bring up and maintain simulation, emulation, and power-aware verification environments. Analyze waveforms, activity dumps, power reports, and execution logs to identify meaningful power-analysis windows. Extract and document windows for peak power, average power, dynamic voltage drop, thermal analysis, and pre-silicon/post-silicon correlation. Debug vector failures, power-state sequencing issues, missing activity, waveform mismatches, and unexpected power behavior. Collaborate closely with DV, Design, Power, Physical Design, Emulation, PTE, and Post-Silicon teams. Maintain traceability between test cases, configurations, waveforms, extracted windows, and delivered vector collateral.
Seniority
Staff/Sr Staff, hands-on IC
