Senior Power Engineer
Core
Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power world class products.
Role type
Senior IC ASIC power engineer
Builds
Digital and/or analog IP blocks and SoCs for Qualcomm's communication and data processing products
Domain
Semiconductors / ASIC Design / Low-power optimization
Deliverable
production ML models
Required skills
RTL power optimization, PowerArtist/PTPX/PowerPro, low-power design techniques (clock gating, power gating), emulation power flow, backend flows (logic synthesis, place-and-route), Python programming, debugging RTL/gate-level power anomalies
Technologies
PowerArtist, PTPX, PowerPro
Responsibilities
Optimize RTL power using switching activity and clock/enable efficiency analysis; Manage dynamic vs. leakage power tradeoffs; Debug RTL or gate-level power anomalies; Build automation scripts and AI/ML-driven analysis flows for power optimization
Seniority
Senior, hands-on IC
