SOC Design Engineer
Core
Design and develop next-generation power control systems and digital front-end ASICs, defining, modeling, and optimizing IP blocks for high-performance, low-power SoCs.
Role type
Senior IC ASIC Design Engineer (Digital Front-End)
Builds
Complex subsystems and IP blocks integrated into System-on-Chip (SoC) architectures.
Domain
Semiconductors / VLSI / ASIC Design
Required skills
RTL design (Verilog/SV/VHDL), Micro-architecture design, Low-power design methodology, Clock domain crossing (CDC), Bus protocols (AHB, AXI, SPMI, I2C, SPI), Formal verification (Cadence LEC), Perl/TCL scripting, Spyglass Lint/CDC checks, RTL to GDS flow knowledge
Preferred skills
Post-Si debug expertise
Technologies
Verilog, SystemVerilog, VHDL, Cadence LEC, Spyglass, DC-Compiler, Prime Time, Perl, TCL
Responsibilities
Develop micro-architecture and implement designs using Verilog/SV; Integrate and deliver complex subsystems to SoC; Collaborate with Systems, Verification, SW, PD, and DFT teams; Analyze reports and run tools for synthesis, simulation, and timing; Create waivers for lint/CDC checks.
Seniority
Senior, hands-on IC
