SOC Implementation Engineer, Lead
Core
Plan, design, optimize, verify, and test electronic systems including Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and DSP systems to launch cutting-edge products.
Role type
Senior IC hardware design implementation engineer (RTL synthesis, DFT, STA)
Builds
High-performance, low-power digital/analog/RF/optical chips and systems
Domain
Semiconductor hardware engineering
Required skills
RTL synthesis, DFT insertion (MBIST, SCAN), static timing analysis (STA), timing constraints setup, logic equivalency checks, ECO flows, gate-level netlist analysis, timing closure
Preferred skills
FPGA design, DSP system design, cross-functional collaboration
Technologies
STA tools, DFT tools, RTL, gate-level netlists
Responsibilities
Perform RTL synthesis to optimize Performance/Power/Area; Insert DFT (MBIST, SCAN) and setup timing constraints; Run static low-power checks on gate level netlists; Verify logic equivalency between RTL-to-Gates and Gates-to-Gates; Setup signoff Static Timing Analysis and ECO flows; Perform timing analysis and constraints debug
