SoC Design Implementation Engineer (Up to Principal Level)
Core
Implement complex SoC, subsystem, and IP designs from RTL through synthesis and handoff to downstream teams, focusing on design constraints, timing analysis, and power-intent implementation.
Role type
SoC Design Implementation Engineer (Up to Principal Level)
Builds
High-quality netlists for Physical Design, Design Verification, DFT, emulation, and signoff teams.
Domain
Semiconductor / Hardware Design
Required skills
RTL-to-netlist transformation, synthesis optimization, timing constraint development, QoR analysis, low-power implementation (UPF), flow configuration, root cause analysis, cross-functional collaboration
Preferred skills
UPF methodology, automation development, mentorship
Technologies
Synthesis flows, UPF, timing analysis tools, RTL, constraints, libraries, build environments
Responsibilities
Support implementation of complex SoC designs from RTL through synthesis; Develop and maintain timing constraints for block, subsystem, and SoC-level designs; Run and debug RTL synthesis to generate clean netlists; Analyze design quality and identify issues affecting timing, power, area, or convergence; Debug tool failures and design-quality issues using logs and reports; Mentor engineers and share best practices in synthesis and implementation methodology
Seniority
Up to Principal Level
