SoC RTL Design Engineer (Up to Principal Level)
Core
Integrate RTL from multiple IPs and subsystems into SoC-level designs, manage synthesis flows, and prepare front-end readiness for downstream implementation.
Role type
Senior IC SoC RTL Design Engineer
Builds
System-on-Chip (SoC) designs and subsystems
Domain
Semiconductor / Hardware Design
Required skills
RTL design (Verilog/SystemVerilog), SoC integration, synthesis flows, timing analysis, clock/reset design, bus protocols (AXI/APH/APB), EDA tools, scripting (Python/Perl/Tcl)
Preferred skills
NoC/interconnect integration, low-power design, formal equivalence, gate-level simulation, flow automation
Technologies
Verilog, SystemVerilog, Python, Perl, Tcl, Shell, EDA tools
Responsibilities
Integrate RTL from multiple IPs and subsystems; Develop top-level RTL wrappers and interconnect structures; Run and debug RTL compile, lint, CDC, and synthesis flows; Analyze synthesis reports for timing, area, and power issues; Collaborate with physical design teams to resolve timing convergence; Support functional equivalence and design-release readiness.
Seniority
Senior, hands-on IC
