SOC Power Architect
Core
Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power world class products, specifically developing next generation power and limits systems for HPC, AI, and automotive systems.
Role type
Senior IC ASIC Power Architect
Builds
Next generation power and limits systems for high-performance SoCs
Domain
Semiconductor / ASIC Design / Power Architecture
Required skills
ASIC design, verification, validation, integration, power and limits system architecture, UPF, power domain crossing, low power design methodology, clock domain crossing, Perl scripting, Python scripting
Preferred skills
Post-Si debug
Technologies
Perl, Python
Responsibilities
Define power and limits system architecture to maximize performance while meeting thermal and electrical constraints; design fast DCVS systems for transient response support; collaborate with cross-functional groups on product execution path; work on micro architecture and interactions with system, SW, and product teams.
Seniority
Senior, hands-on IC
