Staff design Verification Engineer
Core
Staff Design Verification Engineer defining, modeling, designing, optimizing, verifying, validating, implementing, and documenting IP (block/SoC) development for high-performance, low-power products.
Role type
Staff IC design verification engineer (DDRSS IP)
Builds
DDRSS IP across all product tiers for Qualcomm
Domain
Semiconductors / ASIC Design / Digital Verification
Required skills
System Verilog, UVM, Digital design concepts, Bus protocols (AHB/AXI/ACE/ACE-Lite), Multi-core ARMv8 CPU architecture, DDR families (DDR2/3/4/5), Debug, Monitors, scoreboards, sequencers, Functional Coverage
Preferred skills
Post-Si bring-up, HW-SW debug, Silicon debug tool chains
Technologies
Certitude, VC Formal, Fishtail, System Verilog, UVM
Responsibilities
Develop and deploy new tools for validation (Certitude, VC Formal, Fishtail), Debug regression signatures and identify bug fixes, Plan and execute feature additions and mode re-enablement on variants, Create thorough test plans based on specs and standards, Analyze coverage and navigate big test benches
Seniority
Staff, hands-on IC
