SOC Limits Management Architect
Core
Define SoC limits management architecture to balance high performance against physical, electrical, and thermal constraints, bridging hardware IP, system software, and product requirements.
Role type
Senior IC SoC Limits Management Architect
Builds
Next-generation SoCs delivering maximum performance under peak current, power, and thermal constraints while maintaining long-term reliability.
Domain
Semiconductor / Hardware Power Management
Required skills
ASIC design, verification, validation, integration, Power Management, Low-Power Design, Product delivery cycle management, Low-power architectures, Power optimization techniques
Preferred skills
Computer architecture, Power/performance analysis, Peak power management, Power budgeting, In-rush current handling, PDN droop detection and mitigation, Adaptive clock distribution, Aging and process monitors, Power aware floorplanning, Battery technology, Concurrency management, Thermal management, AI
Technologies
Power Telemetry, Estimators, Droop Detectors, Sensing IPs (Voltage, Current, Temperature)
Responsibilities
Define SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.
Responsibilities
Lead cross-functional teams to standardize critical mitigation features, including Power Telemetry, Estimators, and Droop Detectors, across all IP and hardware blocks.
Responsibilities
Drive the long-term evolution of Sensing IPs (Voltage, Current, Temperature) and trigger mechanisms to address escalating current densities and industry trends.
Responsibilities
Design real-time telemetry requirements to monitor silicon behavior and define performance-impact profiles for various mitigation strategies.
Responsibilities
Drive organizational consensus on feature return on investment (ROI) and oversee Post-Silicon Validation to ensure physical silicon behavior aligns with architectural intent.
Seniority
Senior, hands-on IC
