Sr. Staff Packaging Engineer- Process Package Integrity & Bumping
Core
Lead Far-BEOL wafer bumping process integration, qualification, and high-volume readiness for advanced packaging (flip-chip, RDL/fan-out, 2.5D/3DIC) across multiple foundries and OSATs.
Role type
Senior Staff IC Packaging Engineer (Process Integration & Bumping)
Builds
Wafer bumping solutions and advanced packaging structures for silicon chips.
Domain
Semiconductor manufacturing / Advanced Packaging / Silicon Interconnect
Required skills
Far-BEOL bumping process integration, DOE design, failure analysis, statistical data analysis, FMEA, process qualification, supplier management, manufacturing execution, heterogeneous integration flows, test vehicle design, CAD tools (Calibre, Virtuoso, GDS)
Preferred skills
Innovation, creativity, flexible hours, international travel
Technologies
Passivation, UBM, RDL, solder/Cu pillar bump, flip-chip, 2.5D/3DIC, Calibre, Virtuoso, CAD, SiP, GDS
Responsibilities
Define bumping process flows and establish process windows/controls, lead DOE-based optimization, partner with suppliers to improve yield and reliability, lead bumping house/line bring-up and qualification, manage new bumping line ramp-up, interface with foundries and OSATs on process integration, design test vehicles for process characterization.
Seniority
Senior Staff, hands-on IC with project leadership
