ASIC/RTL Design Engineer for High-speed Interfaces
Core
Architect, design, implement, and validate complex mixed-signal IP blocks (SerDes, DDR, die-to-die) for high-performance, low-power mobile, compute, and AI products.
Role type
Senior IC ASIC/RTL Design Engineer (High-speed Interfaces)
Builds
Next-generation interface IPs (SerDes, DDR, die-to-die) integrated into Qualcomm SoCs
Domain
Semiconductor / ASIC Design / High-speed Interfaces
Required skills
Micro-architecture, RTL design, ASIC design flow, SerDes, DDR PHY, PLLs, DFT, STA, CDC analysis, Python/Perl scripting
Preferred skills
Low-power design techniques, Computer architecture, Digital signal processing, Algorithm development
Technologies
VCS, Fusion Compiler, PrimeTime, Power Compiler, DFT Compiler, Spyglass
Responsibilities
Architect digital design of high-speed interface IPs; Develop micro-architecture and implement RTL; Apply advanced techniques to enhance PPA; Utilize ASIC design tools for linting, CDC, DFT, synthesis, FV, and STA; Design and analyze DFT logic; Create design documentation; Collaborate with DV team for verification; Work with PD team for floorplanning and timing closure; Support SoC integration and debug.
Seniority
Senior, hands-on IC
