Next-Gen, High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer
Core
Design and deploy next-generation high-speed HBM/LPDDR/DDR memory controllers for Qualcomm products, interfacing with CPU, GPU, DSP, and multimedia processors.
Role type
Senior IC ASIC Digital Design Engineer (Memory Controller)
Builds
High-speed memory systems (HBM, LPDDR, DDR) integrated into Qualcomm SoCs
Domain
Semiconductor / High-Speed Digital Design
Required skills
RTL coding, ASIC front-end digital design, Hardware Architecture, Synthesis, Timing Closure, Physical Design Support, Gate Level Simulation, Power Analysis, Memory transaction ordering
Preferred skills
LPDDR memory and cache controller, NoC based architectures, HBM memory type designs, On-chip SRAM & L3 cache controller, x86 or ARM CPU/bus architectures
Technologies
RTL, HBM, LPDDR, DDR, NoC, SRAM, L3 cache, x86, ARM
Responsibilities
Develop architecture and design specifications for memory controllers, implement RTL code, debug designs and provide support during integration, contribute to design methodology improvements
Seniority
Senior, hands-on IC
