Senior Verification Engineer / Lead Verification Engineer
Core
Lead verification and validation of complex IPs and SoCs across simulation, emulation, and FPGA prototyping environments.
Role type
Senior IC verification engineer (ASIC/SoC)
Builds
Reusable verification environments, verification plans, and coverage models for IP, subsystem, and SoC-level designs
Domain
Semiconductor hardware design (ASIC/SoC)
Required skills
SystemVerilog, UVM, SVA, constrained-random verification, functional coverage, C/C++, Python, Tcl/Perl/Shell, Git, regression automation, CI/CD, emulation platforms (Siemens Veloce, Cadence Zebu, Palladium), FPGA prototyping (Xilinx/Vivado), protocol verification (LPDDR5/6, PCIe, Ethernet, USB, MIPI, AXI)
Preferred skills
AI-assisted verification, software bring-up, post-silicon debug, automation frameworks
Technologies
SystemVerilog, UVM, Siemens Veloce, Cadence Zebu, Palladium, Xilinx, Vivado, LPDDR5, PCIe, Ethernet, USB, MIPI, AXI, AHB, APB
Responsibilities
Develop and execute verification plans for IP, subsystem, and SoC-level designs; Build reusable verification environments using SystemVerilog, UVM, assertions, scoreboards, and coverage models; Drive functional verification, regression execution, debug, and coverage closure; Debug RTL, testbench, and system-level issues across simulation, emulation, and FPGA platforms; Support software-driven validation, pre-silicon bring-up, and system-level verification; Enable and support emulation and FPGA prototyping environments; Collaborate with design, architecture, firmware, and software teams to ensure product quality and schedule execution; Drive automation, verification methodology improvements, and mentoring junior engineers
Seniority
Senior, hands-on IC with mentorship responsibilities
