CPU Design Verification Principal Engineer
Core
Verify high performance and low power CPUs, focusing on power management, clock gating, power gating, voltage/frequency management, and throttling.
Role type
Principal CPU Design Verification Engineer
Builds
High performance, low power CPU chips for next-generation connected devices
Domain
Semiconductor / Hardware Engineering
Required skills
Power management verification, UPF, simulation, formal verification, assertions, Verilog/SystemVerilog, C/C++, embedded firmware, emulation, FPGA, debug and triage
Preferred skills
CPU architecture and micro-architecture, digital logic design, DFT architecture, JTAG, IEEE1500, MBIST, scan dump, memory dump
Technologies
UPF, Verilog, SystemVerilog, C, C++, FPGA, Emulators
Responsibilities
Develop comprehensive test plans for power management verification, execute test plans using simulation and formal verification, write checkers and assertions, verify power intent using UPF, validate system use cases with architects and software teams, enable verification on emulators and FPGA platforms, debug and triage failures in simulation, emulation, and silicon
Seniority
Principal, hands-on IC
