Senior Lead RTL/Power Engineer
Core
Lead SoC power tasks, develop UPF/CPF for IPs, and perform power analysis/recovery on clocktree/netlists to optimize electronic systems.
Role type
Senior Lead RTL/Power Engineer
Builds
SoC power architecture and low-power designs for cutting-edge mobile products
Domain
Semiconductor / Hardware Engineering / Low Power Design
Required skills
UPF/CPF development, Power analysis (Static/Dynamic), Low power design techniques, Clocktree optimization, Netlist analysis, Multi-power rail architecture
Preferred skills
FPGA/DSP system experience, SoC level power analysis
Technologies
UPF, CPF, PTPX, FPGA, DSP
Responsibilities
Lead SoC Power tasks, Develop UPF/CPF working with IPs, Perform power analysis and recovery on clocktree/netlists, Execute Static/Dynamic Power analysis using PTPX, Define isolation strategy for low power, Design Multi-power rail based Power architecture
Seniority
Senior, hands-on IC
