CPU Physical Design Engineer, Staff
Core
Staff CPU Physical Design Engineer driving RTL-to-GDSII implementation for high-performance Snapdragon CPUs in sub-10nm technologies.
Role type
Staff IC ASIC Physical Design Engineer (CPU)
Builds
High-performance CPU designs for Snapdragon SoCs (Mobile, Compute, IoT)
Domain
Semiconductor / Hardware / CPU Design
Required skills
RTL-to-GDSII implementation, Place & Route (PnR), timing closure, power optimization, physical verification, flow development, scripting (Tcl/Perl/Python), CPU microarchitecture knowledge
Preferred skills
Cadence Innovus, Synopsys Fusion Compiler, PrimeTime/Tempus, SDC constraints, UPF/CPF, formal verification, IR/EM analysis, clock architecture
Technologies
Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, Tempus, Formality, Conformal, Verilog, Tcl, Perl, Python
Responsibilities
Own block-level physical design from RTL/netlist to GDSII; Perform PnR, timing closure, power optimization, and signoff; Develop implementation methodologies and flows; Execute design experiments for QoR improvements; Collaborate with RTL, Synthesis, STA, and Verification teams; Debug timing, power, and congestion issues.
Seniority
Staff, hands-on IC
