GSoC Design Verification Engineer
Core
Verify next-generation Data Center SoCs powering AI, high-performance computing, mobile, and cloud infrastructure products.
Role type
Design Verification Engineer (SoC)
Builds
Scalable verification solutions for complex SoC designs
Domain
Semiconductor / Hardware Engineering
Deliverable
production ML models
Required skills
System Verilog, UVM, constrained-random testing, functional coverage, RTL debugging, AI/LLM frameworks, agent orchestration, RAG pipelines
Preferred skills
Experience with multi-core CPUs, cache coherency, memory subsystems, AI/ML accelerators, high-speed interconnects
Responsibilities
Develop and execute comprehensive verification plans for SoC, subsystem, and IP-level features; Design and implement scalable System Verilog/UVM-based and Processor-based verification environments; Create directed and constrained-random test scenarios; Develop assertions, functional coverage models, and checkers; Debug RTL, testbench, and integration issues; Drive coverage closure using functional and code coverage metrics; Participate in architecture and design reviews; Verify complex Data Center SoC features; Support emulation and acceleration-based verification; Contribute to methodology improvements, automation, reusable verification components, and AI-assisted verification flows; Develop AI agents that automate engineering tasks; Build agent workflows using modern LLM frameworks; Create integrations between AI systems and engineering tools; Develop Retrieval Augmented Generation (RAG) pipelines for system documentation and engineering knowledge.
