CPU Low Power RTL Design Engineer
Core
Develop low-power CPU micro-architecture and RTL designs for high-performance, low-power devices, working closely with chip architects from early product definition through implementation.
Role type
Senior IC RTL Design Engineer (Low Power CPU)
Builds
Low-power CPU micro-architecture and RTL designs
Domain
Semiconductor / CPU Design / Low Power
Required skills
Verilog, System Verilog, UPF (Power Intent), Low Power Analysis, Logic Design, Timing Analysis, RTL Development
Preferred skills
Low Power Microarchitecture Techniques, Physical Implementation of RTL, High-Performance CPU Trade-offs, Scripting (Perl/Python)
Technologies
Verilog, System Verilog, UPF, Conformal Low Power Analysis Tools
Responsibilities
Define power architecture and specifications from high-level exploration to detailed micro-architectural specs; Develop and refine UPF and RTL designs to match power intent; Collaborate with multi-functional teams to implement and validate Power Aware designs from RTL to physical implementation.
Seniority
Mid-Senior, hands-on IC
