Core CPU Physical Design Engineer (Lead/Staff/Sr Staff)
Core
Lead/Staff Physical Design Engineer for high-speed CPU cores, responsible for RTL-to-GDSII implementation, timing signoff, and PPA optimization.
Role type
Senior IC physical design engineer (CPU)
Builds
High-performance CPU cores for mobile and computing platforms
Domain
Semiconductor / Digital IC Design
Required skills
Physical design, Static Timing Analysis (STA), Power Distribution Network (PDN) methodology, Low power flow (power gating, multi-Vt), Deep sub-micron design solutions (leakage, signal integrity, DFM), Tcl/Perl scripting, Block/Chip level design leadership
Preferred skills
High frequency design convergence, Yield bring-up, Cross-functional collaboration
Technologies
RTL, GDSII, FPGA, DSP, Deep sub-micron processes
Responsibilities
Lead block level or chip level Physical Design, STA and PDN activities; Work independently in RTL to GDSII implementation; Resolve issues regarding constraints validation, verification, and physical design; Collaborate with cross-functional teams to meet performance requirements
Seniority
Staff/Sr Staff, hands-on IC
