Senior ASIC Design Engineer, Compute DSP/AI Processors (multiple levels)
Core
Design high-speed, high-bandwidth, low-power digital hardware solutions for Qualcomm Snapdragon DSP Neural Processing Units (NPU) to accelerate AI machine learning, video, and DSP applications.
Role type
Senior ASIC Design Engineer (Compute DSP/AI Processors)
Builds
HW IP for Snapdragon DSP NPU
Domain
Semiconductor / AI / Video Processing
Deliverable
production ML models
Required skills
SystemVerilog, ASIC design, synthesis, functional coverage modeling, assertion-based modeling, CDC/LEC/CLP analysis, micro-architecture definition, design tools (VCS, Synopsys Compiler)
Preferred skills
High-performance processor design, low-power optimization, hardware integration support
Technologies
SystemVerilog, VCS Simulator, Synopsys Compiler, Linting, CDC, LEC, CLP
Responsibilities
Design high-speed, high-bandwidth, low power digital hardware solutions; Resolve architecture, design, or verification problems; Contribute to definition, micro-architecture and documentation of HW IP; Collaborate with verification teams to test, debug, and close coverage; Evaluate synthesis results to verify speed, power, and area targets; Support internal hardware integration and software teams.
Seniority
Senior, hands-on IC
