DSP Application Engineer, Principal
Core
Drive customer adoption and deployment of next-generation DSP in Optical Transceiver and Active Electrical Cable (AEC) solutions for AI and cloud infrastructure.
Role type
Principal DSP Application Engineer (Hardware Applications)
Builds
High-speed connectivity solutions supporting 100G/lane, 200G/lane, and 400G/lane PAM4 technologies for AI clusters, switches, NICs, GPUs, and accelerator platforms.
Domain
Semiconductor, Networking, Optical Communications, AI Infrastructure
Required skills
PAM4 signaling, DSP-based equalization, SerDes architectures, Ethernet connectivity, Signal integrity, Optical communications, Instrumentation automation (Python/C), Root-cause analysis, Eye diagram analysis, BER results analysis, Jitter measurements, Equalization settings, Channel models, IEEE 802.3 compliance testing
Preferred skills
Optical transceiver architecture, Optical component physics (Laser, EML, silicon photonics, Photodiode), RF components (Driver and TIA), Optical transceiver design (schematic/mechanical/thermal/PCB), Hyperscale cloud customer support, DSP algorithms (CTLE, FFE, DFE, adaptive equalization)
Technologies
PAM4, SerDes, Ethernet, Python, C, Oscilloscopes, BERTs, VNAs, IEEE 802.3
Responsibilities
Serve as technical lead for strategic customers deploying Qualcomm DSP-enabled AEC and Optical Transceiver products; Drive customer engagements from architecture evaluation through production deployment; Lead technical design reviews, system bring-up, interoperability testing, and performance optimization; Support integration of Optical Transceiver and AEC solutions into AI clusters, switches, NICs, GPUs, and accelerator platforms; Optimize DSP in the PAM4 link performance across optical channels, electrical channels, cable assemblies, retimers; Lead root-cause analysis across optical channels, DSP, SerDes, PMIC, reference clock, firmware, and PCB channels.
Seniority
Principal, hands-on IC & technical leadership
