CPU Micro-Architecture and RTL Design Engineer (RISC-V)
Core
Design high-performance, low-power CPU micro-architecture and RTL for RISC-V devices, collaborating with architects on product definition and verification.
Role type
Senior IC CPU Micro-architecture and RTL Design Engineer
Builds
High-performance, low-power RISC-V CPU cores
Domain
Semiconductor / CPU Design / RISC-V
Required skills
Microprocessor architecture (fetch/decode, branch prediction, scheduling, register renaming, out-of-order execution, load/store, cache/memory), RTL design (Verilog/VHDL), Logic design principles, Timing and power analysis, Low power techniques, High-performance trade-offs, Scripting (Perl/Python)
Preferred skills
CPU modeling, Waveform debugging tools, Physical design validation (timing, area, reliability, testability)
Technologies
Verilog, VHDL, Perl, Python
Responsibilities
Explore high-performance strategies with modeling teams; Develop micro-architecture specifications from high-level concepts; Own RTL design development and refinement; Support functional and performance verification; Collaborate on physical design implementation and validation.
Seniority
Senior, hands-on IC
