RTL Design -Director(SOC Lead)
Core
Lead next-generation AI and Data Centre SoC architectures (switch and IO chiplets) from high-level system design to micro-architectural partitioning and RTL direction.
Role type
Director-level SoC Lead (Hands-on IC with leadership)
Builds
Dragonfly rack-scale Agentic AI platform, Ethernet switch and IO chiplet programs
Domain
Semiconductor / Hardware Engineering / AI Infrastructure
Deliverable
production ML models
Required skills
SoC design, RTL development (Verilog), micro-architecture, IP dependency orchestration, synthesis convergence, timing closure, cross-IP friction assessment, design-for-convergence principles
Preferred skills
Ultra-high bandwidth data processing experience, low-latency transport expertise, scalable throughput optimization, energy-efficient data movement strategies
Technologies
Verilog, SoC Design, Digital Design
Responsibilities
Define and defend architectural trade-offs, drive milestone discipline across design/verification/implementation, mentor engineers on convergence principles, navigate full design convergence cycle (Architecture to Timing Closure)
Seniority
Director, hands-on IC with strategic leadership
