DFT Engineer (Senior to Staff level)
Core
Architecting and developing DFT methodologies, flows, and verification solutions for complex SoC and IP designs to ensure testability and quality.
Role type
Senior DFT Engineer (IC)
Builds
Integrated RTL-centric DFT environments, automated verification test benches, scan insertion flows, and ATPG retargeting procedures for ASICs and SoCs.
Domain
Semiconductor hardware engineering, SoC design, DFT/ATPG
Required skills
DFT methodologies (scan insertion, BIST, ATPG), RTL design (Verilog/VHDL/SystemVerilog), EDA tools (Siemens, Synopsys, Cadence), scripting (Perl, TCL, Python), static timing analysis, SoC/Block level design
Preferred skills
CoWoS design experience, zero delay/SDF annotated test sequence simulation, CAD automation
Responsibilities
Architecting integrated RTL-centric DFT environments, writing and automating RTL for advanced DFT features, developing automated verification test benches, building IP/SoC level scan insertion flows, creating static timing constraints and waivers
Seniority
Senior, hands-on IC
