CPU Physical Design Timing Engineer (Austin, TX)
Core
Define, develop, and drive CPU timing closure for Oryon CPU Cores using industry standard tools/flows.
Role type
CPU Physical Design Timing Engineer
Builds
Oryon CPU Cores
Domain
Semiconductor / CPU Design
Required skills
TCL/Perl/Python automation, STA setup and signoff, timing analysis and debug across PVT conditions, Primetime/Tempus flow optimization, Spice to STA correlation, root cause analysis of timing miscorrelation, digital flow design implementation (RTL to GDS)
Preferred skills
AOCV/POCV concepts, CTS, timing constraints management, Latch transparency handling, 0-cycle/multi-cycle path handling, Chip-level and Hard-Macro timing convergence, crosstalk noise and Signal Integrity, Layout Parasitic Extraction, ASIC back-end design flows (ICC2, Innovus), device physics
Technologies
PT/Tempus, ICC, Innovus, Primetime, Spice
Responsibilities
STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs; Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus; Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation; Find out the root cause of timing miscorrelation at different design levels in functional and test mode, propose solutions; Evaluate multiple timing methodologies/tools on different designs and technology nodes; Familiar with digital flow design implementation RTL to GDS : ICC, Innovus , PT/Tempus
Seniority
Mid-level, hands-on IC
