RTL Design Engineer - Security /Staff
Core
Develop micro-architecture and RTL design for security-related hardware cores, enabling software teams to utilize these hardware blocks.
Role type
Staff RTL Design Engineer (Security)
Builds
Security cores and hardware blocks for ASIC/SoC
Domain
Semiconductor / Hardware Security
Required skills
RTL design (Verilog/System Verilog), ASIC/SoC design, Linting, CDC, LEC, Cryptography (AES, SHA, GMAC), Database management (Clearcase/Clearquest), Programming (Verilog, C/C++, Python, Perl)
Preferred skills
10+ years ASIC/SoC experience, Cryptography knowledge, Linting/CDC/LEC expertise, Database flows
Technologies
Verilog, System Verilog, Clearcase, Clearquest, Lint, CDC, LEC, AES, SHA, GMAC
Responsibilities
Design micro-architecture for security cores, Enable SW teams to use HW blocks, Run ASIC development tools (Lint, CDC), Report status and communicate progress
Seniority
Staff, hands-on IC
