SoC Design & Synthesis Engineer
Core
Synthesizing large-scale SoC RTL designs into high-quality gate-level netlists ready for Place & Route, optimizing PPA, and supporting functional ECOs for Snapdragon products.
Role type
Senior IC SoC Design & Synthesis Engineer
Builds
High-performance, low-power SoCs for mobile, automotive, and edge AI platforms
Domain
Semiconductor / ASIC Design
Required skills
RTL-to-gate synthesis, gate-level netlist quality checks, timing constraints (SDC), PPA optimization, functional ECOs, debugging
Preferred skills
Architecture and design tools, scripting tools and programming languages, design verification methods
Technologies
Virtuoso, RTL to GDS Flow
Responsibilities
Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development; Create architectures, circuit specifications, logic designs, and system simulations; Collaborate across teams to develop implementation strategies; Evaluate process flow from high-level design to synthesis, place and route, timing, and power use; Utilize tools to execute architecture and design of blocks/SoCs; Write detailed technical documentation
Seniority
Senior, hands-on IC
