Sr. Staff/Principal Engineer - Low Power Chip Architect / System Engineer
Core
Define end-to-end system architecture and drive transistor-level design of ultra-low-power mixed-signal ICs for Robotics and Industrial IoT applications.
Role type
Sr. Staff/Principal Low Power Chip Architect / System Engineer
Builds
Ultra-low-power sensor ASICs for Robotics and IIoT
Domain
Semiconductor / Mixed-Signal IC Design
Deliverable
production ML models
Required skills
Mixed-signal IC design, Transistor-level design, System architecture, Low-power analog design, Behavioral modeling, Pre-silicon verification, Post-silicon bring-up, Sensor fusion, Edge AI integration, Deep submicron CMOS processes
Preferred skills
PhD in Electrical Engineering, Chip Lead experience, Cadence Virtuoso, AMS simulation, Spectre/HSPICE, PDK flows, ESD/reliability standards, Digital design flows, Firmware integration, Embedded interfaces (I2C, I3C, SPI, MIPI), Python scripting
Technologies
MATLAB/Simulink, Cadence Virtuoso, Spectre, HSPICE, Verilog, Python
Responsibilities
Define and support end-to-end system architecture including partitioning across analog, digital, firmware, and system domains; Drive architectural trade-offs across power, performance, noise, latency, and silicon area; Lead feasibility studies and transistor-level design of mixed-signal building blocks including ADCs, DACs, PLLs/DLLs, LDOs, and SerDes; Develop behavioral and system-level models to evaluate noise, linearity, and SNR; Perform comprehensive pre-silicon verification across PVT corners; Support post-silicon bring-up, characterization, and reliability qualification; Collaborate with packaging, test, and system teams to ensure successful productization.
Seniority
Sr. Staff/Principal, hands-on IC architect with technical leadership
