Analog / Mixed-Signal PLL Design Engineer, Senior - Cork, Ireland
Core
Designing low-power, low-voltage analog and mixed-signal integrated circuits for high-speed clocking IP (PLL/DLL/FLL) for Qualcomm SoCs in leading-edge process nodes (3nm+).
Role type
Senior IC analog/mixed-signal design engineer
Builds
High-speed clocking IP (PLL/DLL/FLL) for Mobile, Auto, IoT & Compute SoCs
Domain
Semiconductor / Analog Mixed-Signal IC Design
Required skills
Transistor-level analog/mixed-signal circuit design, Device physics, Analog custom layout, Power distribution networks (PDN), Mixed-signal design flow, SoC top-level integration, IC Design Tools, SPICE simulators, Schematic capture tools, Behavioral modeling in Verilog, Circuit simulation and analysis, Silicon characterization
Preferred skills
Frequency synthesis design, High-speed wireline SerDes, DDR design, Signal integrity in high-speed wireline, Scripting for automation
Technologies
FinFET, Gate-All-Around (GAA), 3nm process nodes, Verilog, SPICE
Responsibilities
Architecture, design, and development of analog/mixed-signal hard macros for high-speed clocking IP; Perform custom circuit design in latest process technologies; Create design specifications and behavioral models; Set up, run, and analyze circuit simulations; Perform quality assurance on hard macros; Deliver hard macros and support customer integration; Perform silicon characterization analysis.
Seniority
Senior, hands-on IC
