Senior Bench Test Engineer, HSIO
Core
Develop test methodologies and characterize high-speed SERDES interfaces (PCIe, USB4, UFS, DP, MIPI, DDR) for highly integrated SOCs.
Role type
Senior IC hardware validation engineer (high-speed interfaces)
Builds
Test solutions and characterization plans for Qualcomm System on Chips (SOCs)
Domain
Semiconductor / Hardware Engineering / High-Speed Interfaces
Required skills
High-speed silicon validation, SERDES interface characterization, electrical compliance validation, first silicon bring-up and debug, power integrity (PI) analysis, signal integrity (SI) analysis, parametric performance analysis, lab equipment operation (Oscilloscopes, TDRs/VNAs, J-BERT), test automation (Python/C#)
Preferred skills
VLSI technologies, CMOS analog/digital circuits, mixed-signal physics, eye diagram analysis, jitter analysis, board design concepts, ASIC device-level characterization
Technologies
PCIe, USB4, UFS, DP, MIPI (DSI, CSI), LP-DDR, PC-DDR, PLLs, DRAM, Python, C#
Responsibilities
Define and execute test methodologies for high-speed interfaces, drive first silicon bring-up and debug, perform technical data analysis of parametric performance, assist in HW design and debug for power and signal integrity, resolve customer issues/RMA debug, conduct specialized analyses (feasibility studies, teardown analyses)
Seniority
Senior, hands-on IC
