Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer
Core
Design and validate RTL for SOC Interconnects, Cache, and Memory Subsystems for Snapdragon platforms.
Role type
Senior IC ASIC Digital Design Engineer
Builds
System-on-Chip (SoC) products for smartphones, PCs, Chromebooks, VR/AR, and automotive.
Domain
Semiconductor / Computer Architecture
Required skills
Verilog/SystemVerilog, Synopsys synthesis, low power design, coverage-based design verification, RTL design, micro-architecture, C/C++/Python programming
Preferred skills
Computer Architecture, Computer Arithmetic, ASIC Design, DV experience, CPU/cache controller design
Technologies
Verilog, SystemVerilog, Synopsys, C, C++, Python
Responsibilities
Micro-architect and design RTL for SOC Interconnects, Caches, and memory subsystems; Optimize hardware design for performance, power, and cost; Evaluate hardware feasibility of complex algorithms; Develop micro-architecture and specifications; Provide verification and debugging activities; Troubleshoot silicon issues.
Seniority
Senior, hands-on IC
