CareerPlan

Design Engineer (Low Power)

Santa Clara, California, United States of AmericaFull-time$190k–$285k2026-09-17 → 2026-11-10

Core

Develop detailed low power micro-architecture and design for WiFi (802.11x) technology and SoC, working from architectural requirements through silicon bring-up and debug.

Role type

Senior IC ASIC Design Engineer (Low Power)

Builds

Low power micro-architecture and SoC designs for mobile, networking, and consumer electronics markets

Domain

Semiconductor / Wireless Technology / SoC Design

Required skills

SoC low power micro-architecture, Power Intent/Implementation, power estimation, RTL implementation, verification, synthesis, timing closure, ARM IP based full chip debug, silicon bring up and debug, AMBA bus protocols (AHB, APB, AXI), multi-domain clocking

Preferred skills

PCIE/USB peripherals, CPU sub system-based design, low power design from project start to volume chip production

Technologies

ARM IPs, WiFi (802.11x), AHB, APB, AXI, PCIE, USB

Responsibilities

Develop technical specifications from architectural and systems requirements, work closely with verification team to develop verification plans, own design through full ASIC development process, perform silicon power measurements and power correlation, execute full chip debug design using ARM IPs

Seniority

Senior, hands-on IC