SoC Front-End Integrator, Senior to Staff (Hsinchu, Taipei)
Core
Integrate RTL and internal IP blocks into SoC designs, ensuring efficient communication and data flow between internal subsystems.
Role type
Senior to Staff SoC Front-End Integrator
Builds
Complex SoC platforms for Industrial and Embedded IoT
Domain
Semiconductor / ASIC Design
Required skills
Verilog/SystemVerilog, SoC integration methodologies, chip-level communication protocols, RTL-to-GDSII flow, timing closure, Python/Tcl/Shell scripting
Preferred skills
Low-power design techniques, AMBA protocols (AXI, AHB, APB), post-silicon validation, EDA tools (Synopsys, Cadence)
Technologies
Verilog, SystemVerilog, Python, Tcl, Shell, AXI, AHB, APB, Synopsys Design Compiler, VCS, Cadence
Responsibilities
Integrate RTL and internal IP blocks into SoC designs; Ensure efficient communication and data flow between internal subsystems; Handle bus/interconnect design (AXI, AHB, APB) and optimize subsystem connectivity; Manage clock/reset domain crossing (CDC/RDC) to ensure reliable synchronization; Collaborate with verification teams to validate subsystem interactions and coverage; Work with physical design teams to achieve timing closure and integration readiness; Debug and resolve integration issues across simulation, emulation, and silicon validation; Support system-level bring-up and performance correlation in post-silicon validation; Drive methodology improvements and automation for SoC integration flow; Provide guidance on interface protocols, integration best practices, and coding styles
Seniority
Senior to Staff, hands-on IC
