WIFI PHY Senior Design Verification Engineer
Core
Verify Wifi and/or Modem PHY layer from TX and RX perspectives for mobile phones, wearables, and IoT chipsets.
Role type
Senior IC design verification engineer (PHY)
Builds
ASIC designs on latest technology nodes
Domain
Wireless communications, VLSI
Required skills
System Verilog, UVM, assertion-based verification, coverage-based verification, constraint random testing, RTL debugging, Verdi, formal/static verification, scripting (Perl/Python)
Preferred skills
Wireless protocols, Modem/Wifi Standards, DSP IP verification, Power Aware verification, GLS
Technologies
System Verilog, UVM, Verdi, Perl, Python
Responsibilities
Develop verification plans and testbenches, write assertions and run simulations to achieve coverage goals, debug RTL/TB issues, collaborate with design and architecture teams, explore innovative DV methodologies
Seniority
Senior, hands-on IC
