RTL Design(Turing-AI/ML)-Sr Engineer/Sr Lead
Core
Designing and implementing RTL for AI/ML subsystems and SoCs, focusing on microarchitecture, low power, and performance optimization.
Role type
Senior RTL Design Engineer (AI/ML Hardware)
Builds
AI/ML subsystems and System-on-Chip (SoC) designs
Domain
Semiconductor Hardware Engineering / AI/ML Infrastructure
Deliverable
production ML models
Required skills
Verilog/System Verilog, Microarchitecture design, Low power design, NoC design, Performance optimization (Bandwidth/Latency), Timing constraints, UPF, CDC/Lint checks, Assertion-based testing, Simulation and waveform debugging
Preferred skills
Master's or Bachelor's degree in EE/CS, 2+ years of hardware design experience
Technologies
Verilog, System Verilog, Simulators, Waveform debugging tools
Responsibilities
Develop microarchitecture and coding strategies to meet PPAS goals; Define block-level design aspects (interfaces, clocking, pipeline); Lead RTL coding and simulation debug; Drive Lint/CDC/FV/UPF checks; Develop assertions for white-box testing.
Seniority
Senior, hands-on IC
