Physical Design Engineer (Engineer up to Principal Level)
Core
Deliver world-class semiconductor solutions by implementing and delivering industry-leading physical designs for complex, high-performance, low-power SoCs and IP blocks from synthesis through final tapeout.
Role type
Physical Design Engineer (IC Implementation)
Builds
Advanced SoC and core design programs across GPU, Multimedia, AI, Compute, Connectivity, Modem, DDR, Audio, and next-generation technologies.
Domain
Semiconductor / ASIC Physical Design
Required skills
Floorplanning, Power planning, Place and route, Clock tree synthesis, Timing closure, Signal integrity analysis, Physical verification, ECO implementation, Design signoff, Automation scripting
Preferred skills
Complete Physical Design Flow expertise, Cadence Innovus, Synopsys Fusion Compiler, Synopsys PrimeTime, MMMC implementation, DFT-aware implementation, RC extraction
Technologies
Cadence Innovus, Synopsys Fusion Compiler, Synopsys PrimeTime, Python, Tcl, Perl, Shell, Linux/Unix
Responsibilities
Execute floorplanning, placement, CTS, routing, timing analysis, and physical verification tasks; Drive timing closure, power optimization, and design convergence; Develop and improve implementation methodologies and automation flows; Lead implementation and signoff of complex subsystems or full-chip partitions; Mentor junior engineers and contribute to technical best practices.
Seniority
Engineer to Principal (2 to 15+ years experience)
