MTS, Interface Pathfinding Hardware Development Engineer
Core
Own characterization for a high-speed interface test-chip program, including planning, bench hardware development, automation, measurement uncertainty, and sim-to-silicon correlation.
Role type
Senior IC hardware development engineer (semiconductor characterization)
Builds
High-speed interface test chips and automated characterization infrastructure
Domain
Semiconductor / Memory and Storage / High-speed interfaces
Required skills
High-speed time-domain measurement, BERT operation, Root Cause analysis, Instrument automation, Frequency-domain fixture de-embedding, First silicon bring-up, Agentic AI workflow construction, Cross-organizational technical leadership
Preferred skills
Silicon photonics, BER-bathtub extrapolation, On-die calibration verification, JEDEC participation (via careerplan.io/jobs/44634713-mts-interface-pathfinding-hardware-development-engineer-at-micron)
Technologies
VNA, TDR, BERT, Pattern generators, Switch-matrix automation, AI-assisted pipelines
Responsibilities
Derive electrical characterization plans from architecture specs, Author observability and test-access requirements, Develop characterization architecture and automated data acquisition, Measure and calibrate characterization hardware, Lead debug tiger teams for sim-to-silicon correlation, Sign tape-out readiness items, Define bench capability and mentor junior engineers, Architect AI-assisted development and characterization pipelines
Seniority
Senior, hands-on IC
