Principal HIG ESD and Latch-up Engineer- HBM - TPG
Core
Define and own chip-level and IP-level ESD and latch-up strategies for HBM DRAM, base die, I/O, TSVs, and die-to-die interfaces to ensure product reliability.
Role type
Principal HIG ESD and Latch-up Engineer (HBM)
Builds
Next-generation HBM solutions for AI and machine learning
Domain
Semiconductor memory (DRAM/HBM) and ESD physics
Deliverable
production ML models
Required skills
ESD physics, latch-up mechanisms, advanced CMOS devices, ESD protection circuits, latch-up prevention techniques, JEDEC/ESDA standards, silicon validation, failure analysis, foundry interface
Preferred skills
HBM/DRAM ESD sign-off experience, SCR-based clamps, distributed ESD networks, rail-based strategies, foundry ESD team collaboration, mentorship
Technologies
HBM, CDM, JESD78, TSVs, I/O, SCR-based clamps
Responsibilities
Define and own chip-level and IP-level ESD and latch-up strategies; Establish ESD and latch-up requirements, targets, and sign-off criteria; Enable ESD protection circuits and latch-up safe layout practices; Lead silicon validation, failure analysis, and correlation; Act as the technical interface to foundries and partner with design, packaging, reliability, and product teams
Seniority
Principal, hands-on IC with mentorship
