DFT Intern
Core
Design for Test (DFT) implementation and verification for ultra-low power System-on-Chip (SoC) designs to improve manufacturing test coverage and quality.
Role type
Design for Test (DFT) Intern
Builds
Ultra-low power semiconductor chips for wearables, medical devices, IoT, and edge AI applications
Domain
Semiconductor / VLSI / Low Power Design
Required skills
Digital logic design, VLSI/ASIC design, CMOS circuits, Verilog/SystemVerilog/VHDL, Linux/UNIX environment, Analytical debugging, Problem-solving
Preferred skills
Scan insertion, ATPG, MBIST, Memory repair, EDA tools, Scripting (Tcl/Python/Shell), Fault models, Low power design concepts
Technologies
Tcl, Python, Shell, Verilog, SystemVerilog, VHDL, EDA tools
Responsibilities
Support low power DFT implementation and verification for SoC designs, Assist with scan insertion and scan chain verification, Assist with MBIST insertion and verification for embedded memories, Analyze DFT rule checking results and resolve design/testability issues, Support test coverage analysis and identify improvement opportunities, Develop and maintain automation scripts, Collaborate with RTL, DFT, DV, and physical design engineers
Seniority
Intern
