Staff Physical Design Engineer
Core
Drive the physical implementation of next-generation semiconductor chips, translating complex microarchitectures into high-performance, power-efficient silicon.
Role type
Staff Physical Design Engineer (IC)
Builds
High-performance, power-efficient silicon chips for edge-to-cloud computing
Domain
Semiconductor hardware / AI systems
Deliverable
production ML models
Required skills
Block-level and top-level physical design, floor-planning, placement, clock tree synthesis (CTS), routing, static timing analysis (STA), timing closure, power grid verification, electromigration and IR drop (EM/IR) analysis, Tcl/Python scripting, low-power design techniques, advanced process node knowledge
Preferred skills
Hierarchical floorplanning, PDK management, foundry tapeout processes
Technologies
Cadence EDA tools
Responsibilities
Drive block-level and top-level physical design including floor-planning, placement, CTS, and routing; Achieve aggressive timing, power, and area (PPA) targets; Perform power grid verification and manage EM/IR analysis; Develop automation scripts in Tcl/Python; Collaborate with physical verification and foundry teams for tapeout
Seniority
Staff, hands-on IC with strategic guidance
