Staff Physical Design Engineer-DPG-LPDDR
Core
Lead end-to-end RTL-to-GDSII implementation for complex SoCs across advanced technology nodes, driving floor planning, P&R, timing closure, and physical signoff.
Role type
Staff Physical Design Engineer (SoC)
Builds
Complex System-on-Chip (SoC) memory and storage solutions
Domain
Semiconductor / VLSI / Memory and Storage
Deliverable
production ML models
Required skills
RTL-to-GDSII implementation, Floor planning, CTS, Place & Route, Timing Closure, Physical Signoff, PPA optimization, Low-power design, STA, SI, EM/IR, DRC, LVS, Tcl/Python/Perl scripting, Technical leadership
Preferred skills
Custom layout design, Analog/mixed-signal integration, AI/ML tools for physical design automation, Generative AI and Agentic AI solutions
Technologies
ICC2, Fusion Compiler, Innovus, PrimeTime, Calibre
Responsibilities
Lead end-to-end RTL-to-GDSII implementation, Drive floor planning and power planning, Own PPA optimization and congestion management, Lead STA/SI/EM/IR/DRC/LVS closure, Define physical design methodologies and automation strategies, Partner with cross-functional teams, Provide technical leadership and mentor engineers
Seniority
Staff, hands-on IC with technical leadership
