Sr. Staff SoC Power & Performance Architect
Core
Architecting power and performance for low-power System-on-Chips (SoCs) from early design through silicon validation.
Role type
Sr. Staff IC SoC Power & Performance Architect
Builds
Power-efficient semiconductor solutions for wearables, medical devices, IoT, and AI edge applications
Domain
Semiconductor / Low-power SoC Design
Deliverable
production ML models | product features
Required skills
Low-power SoC architecture, power analysis & budgeting, silicon debug, Python/TCL scripting, power-aware simulation, architecture specification, process-node tradeoff analysis
Preferred skills
UPF/IEEE 1801 authoring, clocking/reset architecture, Arm Cortex-M/A/RISC-V experience, heterogeneous multicore architectures, high-bandwidth memory topologies
Technologies
Cadence Genus/Joules, Synopsys PrimePower, Siemens PowerPro, Python, TCL, Confluence, JIRA, Git
Responsibilities
Execute pre-silicon modeling, RTL power analysis, and post-silicon correlation; Build and maintain SoC power budgets; Lead architectural debug of power anomalies; Develop automated power modeling infrastructure and regression dashboards; Characterize power states, leakage, and corner behavior on first silicon; Contribute microarchitecture specifications for power management and clocking; Partner with physical design and software teams on power domain partitioning and flows; Support pre-sales and customer use-case power estimation
Seniority
Sr. Staff, hands-on IC with strategic influence
