Staff Design Engineer, HBM Architecture
Core
Architect, design, and optimize high-speed datapath circuitry for next-generation High Bandwidth Memory (HBM) products, focusing on logic-die and core-die architectures to enable industry-leading bandwidth, power efficiency, and reliability.
Role type
Staff IC HBM Datapath Architect
Builds
Next-generation High Bandwidth Memory (HBM) products
Domain
Semiconductor / Memory / High-Speed Digital Design
Deliverable
production ML models | product features
Required skills
High-speed digital datapath design, Digital schematic build, RTL design, Mixed-signal datapath implementation, HBM/DRAM architecture knowledge, Static timing analysis (STA), Timing closure methodologies, Signal integrity control, Power optimization, Multi-channel operation design
Preferred skills
Layout and floorplanning for high-speed datapath, Advanced process-node challenges, Design review and technical mentoring
Technologies
HBM, DRAM, SerDes, SoC, RTL, Schematic, STA
Responsibilities
Architect and design HBM read/write datapath across core and logic die, Develop high-speed low-latency datapath circuits for multi-channel HBM, Optimize datapath designs for bandwidth, power, area, and timing, Design and integrate data reliability features (parity, ECC, redundancy), Collaborate with PHY, DFT, verification, and layout teams, Drive schematic-level and RTL-level datapath implementations including clocking and gating
Seniority
Staff, hands-on IC with strategic oversight