Engineer, Product Engineering (Media Health Reliability), Heteregenous Integration - High Bandwidth Memory
Core
Define and develop reliability stress test flows and plans for High Bandwidth Memory (HBM) products, driving down defect rates through optimized manufacturing test strategies and root cause analysis.
Role type
Senior IC reliability engineer (semiconductor manufacturing)
Builds
HBM products (DRAM architecture)
Domain
Semiconductor manufacturing / Memory storage
Deliverable
production ML models
Required skills
Root cause analysis, Electric Failure Analysis (EFA), Physical Failure Analysis (PFA), CMOS technology, DRAM architecture, Data analysis, Statistics, Python, JMP, Machine learning (regression, classification, anomaly detection, clustering), AI tooling
Preferred skills
Semiconductor devices, Circuit design, Product validation, Project management
Technologies
Python, JMP, Claude code, Agentic AI
Responsibilities
Define and develop reliability stress test flows and plans; Manage qualification execution progress and drive gating issue resolution; Drive down Extrinsic and Intrinsic Reliability (DPM) through optimized test strategies; Debug and identify root causes of device issues using EFA and PFA; Provide recommendations to fab teams for new process conversions to reduce cost and increase yields; Apply machine learning to reliability datasets to segment fails and outliers; Embed AI/automation into reliability workflows as a standard practice.
Seniority
Senior, hands-on IC
