Senior /Staff AMS Layout engineer-DPG-LPDDR
Core
Lead custom analog and mixed-signal layout for critical LPDDR PHY blocks, ensuring robust operation, signal integrity, and silicon-accurate performance at advanced technology nodes.
Role type
Senior IC layout engineer (analog/mixed-signal, high-speed interface)
Builds
High-performance LPDDR memory chips
Domain
Semiconductor, Memory (DRAM), Analog/Mixed-Signal IC Design
Required skills
Custom analog and mixed-signal layout, High-speed interface design (LPDDR/LPDDRx), Signal integrity analysis (skew, impedance, crosstalk), Array-based layout strategies, Physical verification (DRC/LVS/PEX), PPA optimization, Scripting (SKILL/Python/TCL), Mentorship
Preferred skills
AI/ML concepts for layout automation, VXL-compatible flows
Technologies
SKILL, Python, TCL, VXL, LPDDR
Responsibilities
Own and drive custom analog and mixed-signal layout for critical LPDDR PHY blocks; Lead high-speed LPDDR interface layout execution solving complex signal integrity challenges; Architect scalable array-based layout strategies for DQ/DQS byte lanes; Drive integration of custom digital and mixed-signal blocks within the PHY; Establish robust power distribution, grounding, and isolation strategies; Own physical verification and signoff closure (DRC/LVS, parasitic extraction); Drive post-layout optimization and ECOs; Mentor engineers and contribute to layout methodologies.
Seniority
Senior, hands-on IC
