Engineer/ Sr Memory Layout Engineer-DPG-LPDDR
Core
Design and develop full-custom memory layouts for DRAM/LPDDR arrays, focusing on bit cell, row/column decoders, and peripheral integration to enable high-performance data storage solutions.
Role type
Senior IC memory layout engineer (LPDDR/DRAM)
Builds
High-performance DRAM and LPDDR memory arrays and decoder circuits
Domain
Semiconductor manufacturing, VLSI design, memory architecture
Required skills
Bit cell layout creation, Row/Column decoder layout development, Full-custom layout design, Cadence Virtuoso, Calibre DRC/LVS, DRAM/LPDDR architecture, Device physics, Transistor matching, Well and substrate engineering, Parasitic optimization, EM/ESD reliability
Preferred skills
AI/ML for layout automation and optimization
Technologies
Cadence Virtuoso, Calibre
Responsibilities
Create bit cell layouts and match pitch; Develop row and column decoder layouts; Optimize layouts for power, schedule, and quality; Apply device physics for transistor matching and reliability; Independently plan and deliver layout blocks.
Seniority
Senior, hands-on IC
