Director, HBM RTL Design and Integration
Core
Lead a team in the design, integration, and delivery of next-generation HBM SoC logic die, focusing on RTL development and IP integration for AI/ML and high-performance computing systems.
Role type
Director, HBM RTL Design and Integration
Builds
Next-generation HBM SoC logic die
Domain
Semiconductor / Memory / HBM / AI/ML
Deliverable
production ML models
Required skills
SoC RTL design, SoC integration, IP integration, EDA tools, scripting languages (SystemVerilog, Python, TCL), DRAM/HBM systems knowledge
Preferred skills
Tape-out leadership, cross-functional SoC program management, global engineering team management
Technologies
SystemVerilog, Python, TCL, TSMC processes
Responsibilities
Lead SoC RTL design and integration including subsystem partitioning and IP integration; Drive translation of architectural specs into robust RTL implementations; Oversee SoC integration aspects like clocking, reset, and power intent; Establish design methodologies to improve quality and efficiency; Partner with Architecture, Verification, and Physical Design teams; Build and scale a high-performing RTL design team
Seniority
Director, technical leadership & team management
